The present invention relates to a method of making a flash memory cell. More particularly, the present invention relates to an improved method of forming an interpoly dielectric ONO layer of the flash memory cell.
xe2x80x9cFlash memoryxe2x80x9d i.e., electrically erasable programmable read only memory (EEPROM) devices, are electrically erasable, non-volatile memory devices fabricated with tunnel oxides and high voltage transistors for programming and erasing the devices.
Most flash EEPROM cells have a double polysilicon structure with the upper polysilicon layer patterned to form the control gates and the word lines of the structure. The lower polysilicon layer is patterned to form the floating gates. The lower polysilicon layer is deposited on a tunnel oxide, which is thermally grown on a silicon substrate. A dielectric layer separates the two polysilicon layers. The interpoly dielectric can be an oxide-nitride-oxide (ONO) structure. The nitride layer of the ONO structure is a memory nitride with the ability to store a charge and prevent electrons in the floating gate from escaping.
The dielectric ONO structure is formed by depositing a first layer of silicon dioxide. A layer of silicon nitride is then deposited on top of the silicon dioxide. Finally, the second layer of silicon dioxide is formed on the nitride layer. The second oxide layer is typically grown in a thermal oxidation process, such as a steam oxidation, of the nitride layer.
Several problems exist with the way in which the ONO structure is currently formed. First, thermal oxidation of the nitride layer is a slow process. As the second oxide grows, oxygen in the chamber must migrate further through the increasingly thicker second oxide layer to reach the silicon in the nitride layer. In addition, thermal oxidation decreases the thickness of the nitride layer, because the second oxide layer oxidizes silicon atoms in the nitride layer. As a result, the final thickness of the ONO structure can be difficult to determine. With the scaling down of the physical dimensions of the memory cells for next generation high density non-volatile memory devices, it is particularly important to be able to determine accurately the final thickness of the interpolysilicon ONO structure.
One approach is to deposit the second oxide on the nitride layer. Depositing oxide onto the nitride layer is faster than the oxidation process and does not significantly alter the thickness of the nitride layer. However, deposition of the oxide layer provides a second oxide layer that is more susceptible to leakage current. A deposited oxide has inferior material properties compared to a thermally grown oxide, affecting the overall integrity of the ONO structure.
Accordingly, there is a need for an improved method of forming an ONO structure. The method should provide a faster process of forming the ONO structure. In addition, the method should improve the integrity of the ONO structure.
An advantage of the present invention provides a method of forming an ONO structure, which reduces fabrication time without compromising the integrity of the ONO structure. The present invention pretreats the nitride layer prior to deposition of a second layer of silicon dioxide, thereby enabling the second silicon dioxide layer to be formed without significantly altering the thickness of the silicon nitride layer.
In accordance with one embodiment of the present invention, a method of forming a dielectric structure for a flash memory cell includes forming a first layer of silicon dioxide, forming a layer of silicon nitride on the first layer of silicon dioxide, and pretreating the silicon nitride layer. Pretreatment of the silicon nitride layer includes nitridation. The method further includes depositing a second layer of silicon dioxide on the pretreated silicon nitride layer. Nitridation of the silicon nitride can occur in a batch process or in a single wafer tool, such as a single wafer rapid thermal anneal (RTA) tool.
In accordance with another embodiment of the invention, a method of making a flash memory cell is provided. The flash memory cell includes a substrate, a tunnel oxide and a first polysilicon layer. The method includes forming a first layer of silicon dioxide on the first polysilicon layer and forming a layer of silicon nitride on the first layer of silicon dioxide. The silicon nitride layer is then pretreated by nitridation, and a second layer of silicon dioxide is deposited on the pretreated silicon nitride layer.
In accordance with still another embodiment of the invention, a flash memory cell includes a substrate, a tunnel oxide, and first and second polysilicon layers. The tunnel oxide is deposited between the substrate and the first polysilicon layer. The second polysilicon layer is disposed a predetermined distance from the first polysilicon layer. The flash memory cell further includes an ONO structure sandwiched between the first and second polysilicon layers. The ONO structure includes a first oxide layer, a nitride layer formed on the first oxide layer, and a second oxide layer deposited on the nitride layer. The nitride layer of the ONO structure has been pretreated by nitridation prior to deposition of the second layer of oxide.